The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of performing write transactions from a processor to a graphics device.
The performance of a graphics subsystem within a computer system depends in large part on the amount of data a processor can deliver to a graphics device in a given period of time (throughput). In order for data to reach the graphics device, the data typically must be delivered from the processor to a memory controller over a host bus and then from the memory controller to the graphics device over a graphics bus.
The overall throughput from the processor to the graphics device depends on a number of factors, including data transfer rates from the processor to the memory controller. In order to achieve data transfer rates that approach the maximum possible transfer rates, the memory controller typically includes posted write buffers to receive postable data from the processor. Postable data refers to data that may be received by a system device, such as the memory controller, and later passed on to the final recipient of the data. The processor receives notice that the transaction is complete once the memory controller accepts the data. As long as the posted write buffer is available to accept data, the processor can deliver graphics data to the memory controller at rates approaching the maximum possible rates.
When writing data to the graphics device, the processor will typically attempt to perform multiple sequential write transactions to contiguous addresses. In order to maximize data transfer rates between the memory controller and the graphics device, the memory controller may combine these multiple write transactions into longer burst write transactions. Graphics busses such as the accelerated graphics port (AGP) bus support such burst transactions.
In prior computer systems such as the one described, system performance is degraded when the processor issues a postable write transaction request but the memory controller is not able to receive the postable data associated with the postable write transaction request due to unavailability of the posted write buffers. The posted write buffers may become unavailable due to a number of reasons, including the posted write buffers not being able to drain quickly enough when transferring data from the posted write buffers to the graphics bus interface. Other memory controller activities may also impede the draining of the posted write buffers.
When a postable write transaction request cannot immediately be completed by the memory controller due to unavailability of the posted write buffers, prior memory controllers may stall the host bus until the posted write buffers become available. When a second transaction request is issued by the processor, or another host bus agent, and is received by the memory controller while the postable write transaction request is pending, the memory controller may xe2x80x9cretryxe2x80x9d the postable write transaction request in order to service the second transaction request. The xe2x80x9cretryxe2x80x9d response from the memory controller to the processor indicates to the processor that the postable write transaction request must be reissued at a later time.
Frequent retrying of postable write transaction requests can degrade graphics subsystem performance in a couple of different ways. Because a retried transaction request will need to be reissued by the processor, frequent retries will increase the overhead of performing postable write transactions. Also, because retried postable write transaction requests may be completed in a different order than originally requested, the memory controller may not be able to combine multiple out-of-order postable write transactions into longer, more efficient, burst transactions over the graphics bus.
A method and apparatus for improving throughput from a processor to a device is disclosed. The apparatus includes a bus interface unit to receive a first postable write transaction request and a posted write buffer coupled to the bus interface unit to receive data associated with the first postable write transaction request. The apparatus also includes a timeout counter coupled to the bus interface unit. The bus interface unit initiates the timeout counter if the bus interface unit is currently unable to complete the first postable write transaction request due to unavailability of the posted write buffer and if a second transaction request is received. The bus interface unit issues a retry response to the first posted write transaction request upon an expiration of the timeout counter if the posted write buffer remains unavailable.